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GLD - Designing FPGAs Using the Vivado Design Suite 2

Course Details
Length: 21 Hours
Number of Labs: 9
Number of Chapter: 21
Current Version: 2024.2
Number of Demos: 6

Overview

Learn how to build a more effective FPGA design:
The focus is on:
  • Using synchronous design techniques
  • Utilizing the Vivado™ IP integrator to create a sub-system
  • Performing power analysis and optimization to improve the power efficiency of a design
  • Reviewing and analyzing timing reports for a design
This course builds on the concepts from the Designing FPGAs Using the Vivado Design Suite 1 course.
What's New:
All labs have been updated to the latest software versions
CHAPTERS

UltraFast Design Methodology - Design Creation

Synchronous Design Techniques

Resets

Register Duplication

Scripting in AMD Vivado™ Design Suite Non-Project Mode

Using Tcl Commands in the AMD Vivado™ Design Suite Project Flow

AMD UltraScale Architecture Clocking Resources

UltraScale Architecture I/O Resources - F2

Getting Started with Vivado IP Integrator

Designing IP Subsystems Using Vivado IP Integrator: Introduction

Block Design Containers in the AMD Vivado™ IP Integrator - Introduction

Creating and Packaging Custom IP

Using an IP Container

Report Clock Networks

Timing Summary Report

Clock Group Constraints

Introduction to Timing Exceptions

Power Analysis and Optimization Using the AMD Vivado™ Design Suite

Configuration Process

HDL Instantiation Debug Probing Flow

Designing FPGAs Using the Vivado Design Suite 2 Full Course Quiz

OTHER FORMATS

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