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GLD - Designing with VHDL

Course Details
Length: 27 Hours
Number of Labs: 11
Number of Chapter: 28
Current Version: 2023.1
Number of Demos: 1

Overview

This course provides a thorough introduction to the VHDL language.
The emphasis is on:
  • Writing efficient hardware designs
  • Performing high-level HDL simulations
  • Employing structural, register transfer level (RTL), and behavioral coding styles
  • Targeting AMD devices specifically and FPGA devices in general
  • Utilizing best coding practices
What'sNew:
Added new module: Vivado™ Simulator Good Coding Practices (VHDL)
All labs have been updated to the latest software versions
CHAPTERS

Introduction to VHDL

VHDL Design Units

VHDL Objects, Keywords, Identifiers

Scalar Data Types

Composite Data Types

VHDL Operators

Concurrency in VHDL

Concurrent Assignments

Processes and Variables

Control Structures in VHDL: if/else and case

Sequential Looping Statements

Delays in VHDL: Wait Statements

Introduction to the VHDL Testbench

VHDL Assert Statements

VHDL Attributes

Vivado Simulator Good Coding Practices (VHDL)

VHDL Subprograms

VHDL Functions

VHDL Procedures

VHDL Libraries and Packages

Interacting with the Simulation

Finite State Machine Overview - VHDL

Mealy Finite State Machine - VHDL

Moore Finite State Machine - VHDL

FSM Coding Guidelines - VHDL

Writing a Good Testbench

Targeting AMD FPGAs and Adaptive SoCs - VHDL

Designing with VHDL Full Course Quiz

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