SLVR - Designing with Verilog

Course Details

Length: 24 Hours

Number of Labs: 9

Number of Chapter: 36

Current Version: 2023.1

Number of Demos: 2

Overview

This course provides a thorough introduction to the Verilog language.

The emphasis is on:

Writing efficient hardware designs
Performing high-level HDL simulations
Employing structural, register transfer level (RTL), and behavioral coding styles
Targeting AMD devices specifically and FPGA devices in general
Utilizing best coding practices

This course covers Verilog 1995 and 2001.

What's New:

All labs have been updated to the latest software versions

CHAPTERS

Introduction to Verilog

Verilog Keywords and Identifiers

Verilog Data Values and Number Representation

Verilog Data Types

Verilog Buses and Arrays

Verilog Modules and Ports

Verilog Operators

Continuous Assignment

Gate-Level Modeling

Procedural Assignment

Blocking and Non-Blocking Procedural Assignments

Procedural Timing Control

Verilog Control Structures: if-else

Verilog Control Structures: case

Verilog Loop Statements

Introduction to the Verilog Testbenches

System Tasks

Verilog Subprograms

Verilog Functions

Verilog Tasks

Verilog Compiler Directives

Verilog Parameters

Verilog Generate Statements

Timing Checks

Finite State Machines

Mealy Finite State Machines

Moore Finite State Machines

FSM Coding Guidelines - Verilog

Avoiding Race Conditions in Verilog

File I/O - Introduction

File I/O - Read Functions

File I/O - Write Functions

Targeting AMD FPGAs and Adaptive SoCs - Verilog

User-Defined Primitives UDPs

Programming Language Interface

Designing with Verilog Full Course Quiz

OTHER FORMATS

On Demand Trainings

Virtual Classroom

Live Classroom

Questions?

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