SLVR - Designing FPGAs Using the Vivado Design Suite 4

Course Details

Length: 21 Hours

Number of Labs: 10

Number of Chapter: 27

Current Version: 2024.2

Number of Demos: 1

Overview

Learn how to use the advanced aspects of the Vivado™ Design Suite.

The focus is on:

Applying techniques to reduce delay and to improve clock skew and clock uncertainty
Utilizing floorplanning techniques
Employing advanced implementation options
Utilizing AMD security features
Identifying advanced FPGA configurations
Debugging a design at the device startup phase
Utilizing Tcl scripting when using the Vivado logic analyzer in a design
This is the final course in the Designing FPGAs Using the Vivado Design Suite series.

What,s New:

All labs have been updated to the latest software versions.

CHAPTERS

UltraFast Design Methodology - Timing Closure

Hierarchical Design

Incremental Compile Flow

AMD Vivado™ Design Suite ECO Flow

Managing IP in Remote Locations

Timing Closure Using Physical Optimization Techniques

Reducing Logic Delay

Reducing Net Delay

Improving Clock Skew

Improving Clock Uncertainty

Intelligent Design Runs

Power Management Techniques

Introduction to Floorplanning

Design Analysis and Floorplanning

Congestion

Daisy Chains and Gangs in Configuration

Bitstream Security

Vivado Design Suite Debug Methodology

Trigger and Debug at Device Startup

Trigger Using the Trigger State Machine in the Vivado Logic Analyzer

Introduction to the Vivado Store

Debugging the Design Using Tcl Commands

Using Procedures in Tcl Scripting

Using Lists in Tcl Scripting

Using Regular Expressions in Tcl Scripting

Debugging and Error Handling in Tcl Scripts

Designing FPGAs Using the Vivado Design Suite 4 Full Course Quiz

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