GLD - Designing with the Versal Adaptive SoC: Hardware Debug
Course Details
Length:
9 Hours
Number of Labs:
3
Number of Chapter:
8
Current Version:
2026.1
Number of Demos:
0
Overview
This course describes the tools and techniques available to debug AMD Versal™ devices. You will learn about features for debugging the fabric (programmable logic) and the hard blocks. The course also covers ChipScoPy APIs, which provide a Python™ interface to program and debug the Versal devices.
The emphasis of this course is on:
Describing the Versal device design flows
Enumerating the Versal device debug features for programmable logic (PL) and hard block debugging
Debugging the Versal device using different debug IP cores
Using ChipScoPy APIs for hardware debugging
Improving Versal device system performance
This course provides virtual access to a Versal VCK190 Evaluation Platform for performing the lab that requires a board.
What's New:
Design Tool Flow module: Introduced the Vitis™ AI development flow and the Neural Processing Unit (NPU) IP
Hard Block Debug module: Added information on timeline trace and system timeline analysis features
System Integration and Validation Methodology module: Added information on optimizing PL performance through pipelining and floorplanning techniques
All labs have been updated to the latest software versions
