This course provides a system-level understanding of AMD Versal™ adaptive SoC serial transceivers. Transceiver architecture, IP generation, simulation, and implementation are covered. Additional information on PCB design issues is also covered.
The focus is on:
Constructing a system using Versal device serial transceivers by:
Selecting the appropriate IP for an application
Configuring Transceivers Wizard IPs
Using transceiver IP example designs
Simulating and implementing transceiver IPs
Identifying the advanced capabilities of the serial transceivers, including using IBERT and eye scan options
Accessing the appropriate reference material for board design issues involving signal integrity, the power supply, reference clocking, and trace design
All modules have been updated to the new GT flow
All labs have been updated to the latest software versions
New lab: GTM implementation and verification
