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GLD - Designing FPGAs Using the Vivado Design Suite 1

Course Details
Length: 20 Hours
Number of Labs: 10
Number of Chapter: 29
Current Version: 2024.2
Number of Demos: 6

Overview

This course offers introductory training on the AMD Vivado™ Design Suite and demonstrates the FPGA design flow for those uninitiated to FPGA design.
The course provides experience with:
  • Creating a Vivado Design Suite project with source files
  • Simulating a design
  • Performing pin assignments
  • Applying basic timing constraints
  • Synthesizing and implementing
  • Debugging a design
  • Generating and downloading a bitstream onto a demo board
What,s New:
All labs have been updated to the latest software versions
CHAPTERS

Introduction to FPGAs

AMD FPGA and Adaptive SoC Portfolio

Introduction to the AMD Vivado™ Design Suite

Introduction to the Tcl Environment

AMD Vivado™ Design Suite Project-Based Mode

AMD Vivado™ Design Suite Non-Project Based Mode

UltraFast Design Methodology - Board and Device Planning

RTL Development

Behavioral Simulation

AMD Vivado™ IP Flow

AMD Vivado™ Synthesis and Implementation and Bitstream Generation

Basic Design Analysis in the Vivado IDE

Vivado Design Rule Checks

Introduction to AMD Vivado™ Reports

Introduction to Clock Constraints

Generated Clocks

I/O Constraints and Virtual Clocks

Timing Constraints Wizard

Static Timing Analysis (STA)

SetUp and Hold Violation Analysis

AMD Vivado™ Design Suite IO Pin Planning

Power Estimation Using XPE

Understanding Design Powers - F1

AMD Versal™ Adaptive SoC Power Design Manager_F1

Introduction to FPGA Configuration

Introduction to the AMD Vivado™ Logic Analyzer

Introduction to Triggering

Debug Cores

Designing FPGAs Using the Vivado Design Suite 1 Full Course Quiz

OTHER FORMATS

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