PLT - Designing with the UltraScale and UltraScale+ Architectures
Course Details
Length:
27 Hours
Number of Labs:
13
Number of Chapter:
16
Current Version:
2024.2
Number of Demos:
2
Overview
This course introduces the UltraScale™ and UltraScale+™ architectures to both new and experienced designers.
The emphasis is on:
Introducing CLB resources, clock management resources (MMCM and PLL), global and regional clocking resources, memory and DSP resources, and source-synchronous resources
Describing improvements to the dedicated transceivers and Transceiver Wizard
Reviewing the Memory Interface Generator (MIG) and DDR4 memory interface capabilities
Migrating existing designs and IP to the UltraScale architecture with optimal use of the Vivado™ Design Suite
What,s New:
All labs have been updated to the latest software versions.
