Learn how to apply UltraFast Design Methodology timing closure techniques and to achieve timing closure for a given design. The emphasis of this course is on:Applying initial design checks and reviewing timing summary...
Provides an introduction to SystemVerilog constructs for verification.This course covers:Writing testbenches to verify a design under test (DUT) utilizing the constructs available in SystemVerilogReviewing object-orie...
With Versal, Xilinx offers the first highly integrated chip series in the new ACAP family -Adaptive Compute Acceleration Platform. The Versal Chips have a heterogeneous architecture with MPSoC, FPGA, PCIe Connectivity...
This is Session 4 in the Versal Adopter Series -Topics Include:Programming the A72, R5F and Platform Management ControllerRunning AIE graph code and RTP (run-time-parameters) on PSOverview of PS instruction set-archit...
This is Session 3 in the Versal Adopter Series - which covers creating efficient chip-level communication schemes.Topics Include:NoC resources and programmingStructure, data-packeting, managing CDCsQoS assignments and...
VHDL for Designers (Xilinx) prepares the engineer for practical project readiness for FPGA designs. While the emphasis is on the practical VHDL-to-hardware flow for FPGA devices, this module also provides the essentia...
This course provides experience with using the Vitis™ Model Composer tool for model-based designs.The course provides experience with:Creating a model-based design using HDL, HLS, and AI Engine library blocks along wi...
This course demonstrates timing closure techniques, such as baselining, pipelining, synchronization circuits, and optimum HDL coding techniques that help with design timing closure. This course also shows you how to d...
This course demonstrates timing closure techniques, such as baselining, pipelining, synchronization circuits, and optimum HDL coding techniques that help with design timing closure. This course also shows you how to d...
