This four-day LIVE Online Training (LOT) course is structured to provide FPGA HW, SW and system architects with an overview of the capabilities and support for the Zynq UltraScale+ MPSoC family.
Learn about the AMD Versal™ adaptive SoC architecture building blocks, such as the programmable logic, high-speed I/O, clocking, processing system, AI Engines, and the programmable network on chip (NoC). Also learn ho...
This course helps you to learn about Versal Adaptive SoC architecture and design methodology.The emphasis of this course is on:Reviewing the architecture of the Versal Adaptive SoCDescribing the different engines avai...
This course helps you to learn about Versal™ Adaptive SoC architecture and design methodology. The emphasis of this course is on:Reviewing the architecture of the Versal Adaptive SoCDescribing the different engines av...
This course describes the tools and techniques available to debug AMD Versal™ devices. You will learn about features for debugging the fabric (programmable logic) and the hard blocks. The course also covers Chip ScoPy...
Thiscourse introduces the features and capabilities of the PCIe® and Cache CoherentInterconnect blocks in the AMD Versal™ adaptive SoC architecture. Learn how toimplement a Versal device PCI Express® solution in custo...
This course provides a system-level understanding of power and thermal issues related to designing with the AMD Versal™ adaptive SoC. PCB design considerations for the Versal devices are also covered. The emphasis of ...
Explore the AMD Versal™ adaptive SoC heterogeneous architecture containing a programmable network on chip (NoC) and AI Engines and learn how to use different design tool flows targeting Versal devices. Gain knowledge ...
This course provides an overview of the hard block capabilities for the AMD Zynq™ UltraScale+™ RFSoC family with a special emphasis on the RF Data Converter and Soft-Decision FEC blocks.The focus is on:Describing the ...
This course provides a thorough introduction to the Verilog language. The emphasis is on: Writing efficient hardware designs Performing high-level HDL simulations Employing structural, register transfer level (RTL), a...
