Expert VHDL Design (2 days) is for design engineers wishing to deepen their knowledge of RTL synthesis using VHDL, and to improve their VHDL coding style with design maintainability and re-use in mind. Design for Veri...
Expert VHDL Verification (3 days) is for design engineers and verification engineers involved in VHDL test bench development or behavioral modelling for the purpose of functional verification.
Fundamentals of SystemC prepares you for the practical use of SystemC for transaction-level modelling. The class describes the core SystemC v2.2 class library and its application for system modelling, virtual platform...
Agile and collaborative software development flows are gaining popularity as they result in more builds, tests, and integrations as well as faster delivery and deployment. Hence, the code is in a »release-at any time ...
This course provides a thorough introduction to the Vitis™ High-Level Synthesis (HLS) tool.The focus is Covering synthesis strategies and features,Applying different optimization techniques,Improving throughput, area,...
IC Verification with Python and cocotb teaches how to use coroutine-based co-simulation testbench (cocotb), a Python-based simulation environment, to carry out RTL verification. Python is pervasive: often taught as a ...
This course covers the fundamentals of the PCI Express® protocol specification.The focus is on:Learning about the typical PCIe® architecture, including data space, data movement, and the most commonly used Transaction...
This course is designed to provide expert guidance on developing a Power Distribution Network to meet the challenges posed by today’s high-speed digital ICs with demanding power requirements. You will learn how to ach...
Practical Deep Learning offers in-depth,hands-on training in deep learning for engineers and programmers. The course is intended to meet the needs of competent professionals already working as engineers or computer pr...
