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Classroom - Designing with Verilog

This course provides a thorough introduction to the Verilog language.

The emphasis is on:
  • Writing efficient hardware designs
  • Performing high-level HDL simulations
  • Employing structural, register transfer level (RTL), and behavioral coding styles
  • Targeting AMD devices specifically and FPGA devices in general
  • Utilizing best coding practices This course covers Verilog 1995 and 2001. 

7/27/2026 - 10/27/2026
Time Zone : (GMT-08:00) Pacific Time (US & Canada)
Seats Remaining : 10
Venue : AUT Vienna - So-Logic Office
Address : Rosengasse 29,Gerasdorf / Kapellerfeld,AUSTRIA
10/5/2026 - 10/7/2026
Time Zone : (GMT+09:00) Seoul
Seats Remaining : 9
Venue : KOR, Seoul - Wedu Office
Address : #B820, Tera tower 2, 201 Songpa-daero, Songpa-gu,Seoul,SOUTH KOREA
3/15/2027 - 9/22/2027
Time Zone : (GMT-08:00) Pacific Time (US & Canada)
Seats Remaining : 10
Venue : AUT Vienna - So-Logic Office
Address : Rosengasse 29,Gerasdorf / Kapellerfeld,AUSTRIA
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