This course provides hardware designers with an overview of the capabilities and support for the AMD Zynq™ UltraScale+™ MPSoC family from a hardware architectural perspective.
The emphasis is on:
Identifying the key elements of the application processing unit (APU) and real-time processing unit (RPU)
Reviewing the various power domains and their control structure
Illustrating the processing system (PS) and programmable logic (PL)connectivity
Utilizing QEMU to emulate hardware behavior
3/30/2026 - 3/31/2026 Time Zone : (GMT+01:00) Amsterdam, Berlin, Bern, Rome, Stockholm, Vienna Seats Remaining : 6 Venue : NLD - Heesch - CoreVision Headquarters Address : Cereslaan 24,Heesch,NETHERLANDS
6/18/2026 - 6/19/2026 Time Zone : (GMT+01:00) Amsterdam, Berlin, Bern, Rome, Stockholm, Vienna Seats Remaining : 6 Venue : NLD - Heesch - CoreVision Headquarters Address : Cereslaan 24,Heesch,NETHERLANDS
